Field of the Invention
Embodiments of the present invention relate generally to integrated circuit chip packaging and, more specifically, to an integrated circuit package with a conductive grid formed in a packaging substrate.
Description of the Related Art
In the packaging of integrated circuit (IC) chips, it is generally desirable to minimize the size and thickness of chip packages. In mobile computing devices, such as smart phones, laptop computers, electronic tablets, and the like, it is particularly desirable to minimize the thickness of IC packages, so that such mobile devices can be further reduced in size and weight. One component in an IC package that directly affects IC package thickness is the packaging substrate.
The packaging substrate is a component of the chip package designed to route power, signal, and ground interconnects between an IC chip in the chip package to external electrical connections, such as a ball-grid array, for connecting the packaged IC chip to a printed circuit board. To this end, a packaging substrate typically includes electrically conductive traces formed in one or more layers on a surface of the packaging substrate. These electrically conductive traces are typically metallic, and therefore have a significantly greater coefficient of thermal expansion (CTE) than that of surrounding materials of the packaging substrate, such as the substrate core and build-up layers. Due to of this mismatch in CTE, when an IC package reaches operational temperature, warpage of the IC package can occur unless the packaging substrate is sufficiently rigid. Consequently, because packaging substrate rigidity is a function of packaging substrate thickness, reducing thickness of an IC package by reducing packaging substrate thickness can result in unacceptable warpage of the IC package during operation.
Accordingly, there is a need in the art for a thinner packaging substrate that does not undergo undo warpage during use.